1. Field of the Invention
The present invention relates to an insulated gate field effect transistor and more particularly to a short channel insulated-gate field effect transistor.
2. Description of the Prior Art
In conventional insulated-gate field effect transistors which are a basic component of MOSLSI (metal oxide semiconductor large scale integration), with the reduction of the length between the source and drain formed on the semiconductor substrate at a distance, the channel length, threshold voltage, far example are markedly reduced and also such parameters are greatly affected by the dimensional precision of the channel length.
As a solution to this problem, a proposal has been made to reduce the planar dimension of the channel length and also to reduce the sectional dimension of each element in the same proportion. However, according to this proposal, extremely small values are required for the dimensions such as the thickness of the gate insulating film, the depth of the source and drain, etc., with resultant very severe fabricating condictions and markedly reduced yield of MOSLSI, etc.
Moreover, it has also been proposed to form opposing sides of the source and drain into the shape of a wedge or an arrowhead. However, according to the IBM Technical Disclosure Bulletin, Vol. 16, No. 2 July, 1973, P. 652, "Reduction of the Small Channel Effect in an IGFET Structure, the practical application of the above proposal has failed due to serious deterioration of the power gain as well as an inability to permit free selection of the power gain.
On the other hand, a proposal (U.S. Pat. No. 3,600,647 P. V. Gray) has been made to form a shallow high conduction layer over the entire area of the channel region by means of ion implantation, etc. in order to prevent a threshold voltage drop resulting from the shortening of the channel length. However, this proposal is ineffective for the elimination of the dependency of the threshold voltage on the channel length precision.